I can't help but think of a super-charged power booster in video games when I hear the term "SuperSpeed USB." The specification is currently defined at 10 Gbit/s SS USB 0.7 DRAFT, and has a 10 Gbit/s data rate. Draft 0.7 is compatible with existing 5 Gbit/s and new 10 Gbit/s USB 3.0 hubs and devices, as well as USB 2.0 products. Check out this short ...
High-speed digital design is a practice that requires a lot of expertise and perhaps a little good luck from time to time -- and it would not be possible without a technology ecosystem that itself is a wonder to behold.
My initial idea for this blog was to honor innovations (and, by extension, innovators) that have played critical roles in bringing the ...
In a previous blog I questioned the need for creating more high-speed interfaces, but I think it is clear to most people that the interface between the processor and the memory is perhaps the biggest problem that most systems face these days. If that interface could be improved, then the processors could get a lot more accomplished, which in turn may put ...
We're informed in the DesignCon call for papers that "product promotion in a paper, panel, or tutorial proposal will lead to rejection of the proposal." Actually, there is a place for commercial content; what there is no place for are commercials!
Commercial content should be restricted to how products work. Exposing new techniques in an open forum to ...
Barry J. Sullivan, Director, Program Development, International Engineering Consortium, 5/16/2013 Comment now 20 comments
I read a nice Mother's Day piece the other day by Suzanne Deffree describing how she is nurturing her young son's inclination toward engineering. It reminded me of my mother's practice of saving old radios and other small appliances for me to take apart (unplugged, of course) and discover their inner workings.
For a while it seemed as if serial communications were the direction that almost everything was going. There were no parallel connectors coming out of the PC anymore, and pin limitations on many chips were forcing high speed I/O to resort to using SerDes interfaces. While a few parallel interfaces remain, such as the processor bus and PCI, the writing on ...
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archived
4/9/2013 1:00:00 PM
High speed digital chip-to-chip link performance is often limited by jitter in the multigigabit per second regime. It is a surprising fact that jitter can actually be amplified by a lossy channel even when the channel is linear, passive, and noiseless. In this webcast we will cover the basics of jitter amplification and show you how to accurately analysis the effect in your system using ADS Channel Simulator.
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