Slides: DesignCon 2013: Challenges with Jitter, 3 hour tutorial
Information Resources 3/25/2013
As signal speeds have increased measuring jitter hasn't become any easier, in fact, it’s become even more difficult. Most designers have been measuring jitter for most of their careers; however, these slides will cover how signal parameters (jitter distribution, noise/slew rate, crosstalk, pattern type) and test equipment (clock recovery model, frequency response, intrinsic jitter and noise) can cause jitter measurements to be different.
Slides: DesignCon 2013: Making DDR4 Work For You, 3 hour tutorial
Information Resources 2/19/2013
Most current on-board and cable communication systems are based on differential signaling. Engineers try to design these systems with as much symmetry as possible. In this session, we explore relative humidity and temperature effects on PCB boards with differential signaling. Of particular interest is mode conversion, since this increases unwanted RF radiation.
Video: PCI EXPRESS® 3.0 Introduction and Overview
Information Resources 12/4/2012
Rick Eads, Board of Directors for PCI-SIG®, talks briefly about the recently published, PCI EXPRESS® 3.0 specification. He outlines the challenges and hints every designer should know.
Application Note: When is it time to transition to a higher bandwidth Oscilliscope?
Information Resources 12/2/2012
Since most of us must work within constrained capital equipment budgets, engineers tend to purchase test equipment that has just enough performance to meet their current needs. So how do we determine how much bandwidth is required for today's projects, and when do we know when it is time to "move up"?
Application Note: FPGA prototyping
Information Resources 12/1/2012
This application note outlines a design flow for Field Programmable Gate Array (FPGA) prototyping, using the Agilent SystemVue software, as well as third-party applications that integrate well with SystemVue.
White Paper: Designing Scalable 10G Backplane Interconnect Systems Utilizing Advanced Verification Methodologies
Information Resources 11/29/2012
The design and implementation of high-speed backplanes requires substantial effort both in pre-prototype modeling and post-prototype testing and measuring. This paper presents techniques for design which significantly reduce modeling requirements for the design of high-speed backplanes in conjunction with advanced testing techniques which provide maximum channel characterization with the minimum amount of time.
Application Note:Debugging Hi-speed USB 2.0 Serial Buses in Embedded Designs
Information Resources 11/28/2012
R&D testing and verification of physical layer characteristics of embedded designs with integrated USB interfaces is extremely important to ensure reliable operation of end-products. Simply selecting USB components, integrating them into an embedded design, and then hope that everything functions is not good enough. Even if the system appears to function, how much margin does it have? Or how does it perform under various environmental conditions such as temperature or humidity?
Application Note: Maximizing DDR BGA probe Bandwidth for Superior Signal Fidelity
Information Resources 11/27/2012
The use of BGA probes for probing DDR DRAM is becoming more popular and almost a requirement as memory design gets more complex and compact and data rate gets higher. DDR3 and DDR4 data rate is increasing from 800MT/s to possibly 3200MT/s. Memory system designers now have huge concerns on current DDR BGA probing design meeting the high bandwidth requirement for best signal fidelity. View this application note for more information.
Application Note: 6 Hints for Better SATA and SAS Measurements
Information Resources 11/16/2012
Failures in signal integrity are correlated to other failures, including marginal timing relationships, protocol violations, jitter issues, and errors from other buses. This application note will highlight a few of the methods that can help you characterize, validate and debug your designs faster.
Application Note: Using PrecisionProbe and PrecisionCable for Ultimate Accuracy
Information Resources 11/15/2012
The ideal way to insure the best accuracy for a probe is to perform a calibration of its response in the configuration that it will be used (i.e. tip span, orientation, etc) before critical measurements are made. This is usually done for DC gain and offset, but hasn't typically been done for response versus frequency (i.e. the "AC" response). Learn more about the recent the ability to perform an AC calibration of probes.
Application Note: Using De-embedding Tools for Virtual Probing
Information Resources 11/14/2012
With today’s high levels of component and platform integration, measuring signals that can’t be physically accessed is becoming the norm. Determining S-parameters with Agilent’s EM field solvers can provide virtual measurement capability when direct measurement is not possible
White Paper: Crossing the Digital-Analog Divide
Information Resources 11/13/2012
As data rates exceed 10 Gb/s, this differential lane skew approaches the length of individual bits and the situation deteriorates. Interference, especially crosstalk, can be a detrimental to digital designs. This application note will walk through these challenges and solutions.
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If one morning an imaginary supreme-engineering-being woke up and decided there should be a discipline known and high-speed digital design, what kind of ecosystem would have to be built?
The interface between the processor and the memory is perhaps the biggest problem that most systems face these days.
DesignCon papers can’t be commercials, but that doesn’t mean you can’t air out the techniques used in your products!
We need to inspire young people to become engineers.
We still need serial interfaces for going off chip, but it would appear that parallel interfaces are about to make a revival.
archived
4/9/2013 1:00:00 PM
High speed digital chip-to-chip link performance is often limited by jitter in the multigigabit per second regime. It is a surprising fact that jitter can actually be amplified by a lossy channel even when the channel is linear, passive, and noiseless. In this webcast we will cover the basics of jitter amplification and show you how to accurately analysis the effect in your system using ADS Channel Simulator.
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