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Barry J. Sullivan

Does Moore Matter?

Barry J. Sullivan
Sunil Kakkar
Sunil Kakkar
11/21/2012 2:23:55 AM
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I don't think that it matters today
Today, the processor is no longer a bottleneck.  EEs have succeeded in designing what the architects dreamt of. Verification engineers also have been successful in verifying these nightmares. CPUs today are superscalar, have speculative execution, conform to  a VLIW architecture and have several layers of coherent caches. They pack enough Ghz.  The hitch now lies in the speed of the peripherals and the interconnect buses. Most of the operations in modern gadgets/devices do not involve supercomputing. They involve moving data from point A to point B.  These so called transactions happen concurrently - several of them - through a criss crossed network of multiple masters and slave devices spanning several buses and different interconnect protocols. The transactions must cross through different clock domains, before reaching their destination.  It is the integrity of these packets and their timely delivery which is at stake.  It is in this area, where the focus is on the design of a fully functional SOC which is stitched together from more basic IPs, each one of which has been verified in seclusion.  This is where the major challenge is - How to integrate these IPs correctly and verify them for concurrent transactions that are totally unpredictable, what with asynchronous interrupts and bus errors.  It is this aspect of designing a SOC, which should take centrestage.

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4/9/2013 1:00:00 PM

High speed digital chip-to-chip link performance is often limited by jitter in the multigigabit per second regime. It is a surprising fact that jitter can actually be amplified by a lossy channel even when the channel is linear, passive, and noiseless. In this webcast we will cover the basics of jitter amplification and show you how to accurately analysis the effect in your system using ADS Channel Simulator.
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