Re: I am a Chip Design Verification Engineer and I am proud of it
Martin,
Per Wikipedia, http://en.wikipedia.org/wiki/Formal_verification
Verification and validation
Verification is one aspect of testing a product's fitness for purpose. Validation is the complementary aspect. Often one refers to the overall checking process as V & V.
- Validation: "Are we trying to make the right thing?", i.e., is the product specified to the user's actual needs?
- Verification: "Have we made what we were trying to make?", i.e., does the product conform to the specifications?
The verification process consists of static/structural and dynamic/behavioral aspects. E.g., for a software product one can inspect the source code (static) and run against specific test cases (dynamic). Validation usually can be done only dynamically, i.e., the product is tested by putting it through typical and atypical usages ("Does it satisfactorily meet all use cases?").
Re: I am a Chip Design Verification Engineer and I am proud of it
Martin,
Thanks a lot for your encouraging attitude and inspiring words for Shachi.
Sunil
Re: I am a Chip Design Verification Engineer and I am proud of it
Sunil,
Wonderful story about your son. Every now and then, we run into inspiring stories like this one. It reminds me of Shay Edwards, a high school student from Southern Calif. Shay was making presentations at the Measurement Science Conference when just a sophomore.
One of the requirements for graduation from my undergraduate college was (and still is) the completion of a project that relates technology to society. Mine, in the 1970s, was to develop seminars for elementary school treachers on how to teach the metric system to their students.
Re: I am a Chip Design Verification Engineer and I am proud of it
How do you define the differences of verification, validation, and characterization? Sounds like the making of a good blog.
I am a Chip Design Verification Engineer and I am proud of it
http://ireport.cnn.com/docs/DOC-872803
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4/9/2013 1:00:00 PM
High speed digital chip-to-chip link performance is often limited by jitter in the multigigabit per second regime. It is a surprising fact that jitter can actually be amplified by a lossy channel even when the channel is linear, passive, and noiseless. In this webcast we will cover the basics of jitter amplification and show you how to accurately analysis the effect in your system using ADS Channel Simulator.
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